The PCB layer stack-up defines how copper, dielectric, and prepreg layers are arranged within a multilayer board. Getting the stack-up right is foundational to signal integrity, impedance control, EMI performance, and manufacturability. Getting it wrong can result in a board that works poorly — or not at all.
Why Stack-Up Matters
In a simple two-layer board, the stack-up is trivial: copper on top, dielectric in the middle, copper on the bottom. But as layer counts increase, the decisions multiply: Which layers carry power planes? Where do high-speed signals route? How thick are the dielectric cores? Each choice cascades into others.
The Standard 2-Layer Stack
A standard 1.6 mm 2-layer board consists of:
- Top copper layer (typically 1 oz, 35 µm)
- FR-4 core (1.55 mm)
- Bottom copper layer (typically 1 oz, 35 µm)
Simple and inexpensive. The trace impedance for a standard 6 mil microstrip trace on this board is approximately 50 Ω — suitable for many general-purpose designs.
Moving to 4 Layers
The jump from 2 to 4 layers is one of the most impactful upgrades available to a PCB designer. A typical 4-layer stack-up looks like this:
- Layer 1 (Top): Signal routing
- Layer 2: Ground plane (GND)
- Layer 3: Power plane (VCC or split power)
- Layer 4 (Bottom): Signal routing
The adjacent ground plane on Layer 2 provides a controlled impedance reference for microstrip traces on Layer 1, dramatically improving signal integrity. The close coupling between Layer 2 (GND) and Layer 3 (Power) also creates distributed decoupling capacitance across the entire board — free.
6-Layer and Beyond
As complexity grows, additional layers allow signal separation, dedicated power distribution, and tighter impedance control. A common 6-layer arrangement routes high-speed differential pairs on inner layers between two ground planes, minimising crosstalk and radiated emissions.
Key Stack-Up Design Principles
- Pair every signal layer with an adjacent reference plane. A signal layer without a nearby ground reference will have uncontrolled impedance and radiate more.
- Keep power and ground planes adjacent. The close coupling provides natural decoupling capacitance.
- Use symmetrical stack-ups. Asymmetric copper distribution causes bowing during lamination. Your fabricator will flag this issue during DFM.
- Match dielectric thickness to your impedance targets. Thinner dielectric = tighter coupling = lower impedance. Use an impedance calculator or ask your fabricator for standard stack-up options.
HDI: High-Density Interconnect
HDI boards add laser-drilled microvias, blind vias, buried vias, and via-in-pad to achieve extremely high component density. HDI is common in smartphones, wearables, and aerospace electronics. The manufacturing cost is higher, but HDI enables BGA packages with pitch below 0.4 mm and dramatically reduces board size.
At EazyPCB, we support standard multilayer up to 20 layers and HDI designs with blind/buried vias and via-in-pad. Contact our team if you need stack-up recommendations for your specific design.
